1. Field of the Invention
This invention relates to multi-layered printed circuit boards for mounting and interconnecting the terminals of electronic components. More specifically, the invention resides in an improvement in such boards wherein high speed signals are routed along a path having the characteristics of a transmission line.
2. Brief Description of the Prior Art
Multi-layered printed circuit (PC) boards are generally of two types. Both types may have alternating layers of conductive and insulating material, the conductive layers carrying power, ground, and/or signals to be routed between the pins of the electronic components mounted on the board.
A first type of multi-layered printed circuit board, referred to herein as a panel board, uses a number of sockets and discrete wiring. The class of panel boards include:
Stitch-Wiring, where the interconnecting wires are welded to either the sockets or to pads on the printed circuit board which in turn are connected to the sockets; PA1 IDC, or Insulation Displacement Connections, in which the insulated wires are forced down into grooves or forks on the wiring end of the sockets; PA1 Soldering, where the insulated wires are soldered, directly or indirectly, to the sockets; and PA1 Wire-wrap, described in Leary et al., U.S. Pat. No. 4,494,172 and others, where socket terminals are held in mounting holes in the insulative layers of the board. The socket terminals have sockets on one end for insertion of leads of electronic components, and posts on the other end for wrapping wire to make connections. PA1 1. Wire over ground; PA1 2. Microstrip; and PA1 3. Strip line. PA1 1. Cluster time critical logic elements reasonably close together--to within 50 to 70 mm of each other; PA1 2. Insure that the length of the stubs or lines attached to the clock's transmission line are limited to a maximum of 50 mm to 75 mm (2 inches to 3 inches). The desire here is to make sure that any reflections back down the stub take place during the clock's rise or fall time; PA1 3. Distribute the clock loads evenly across the various clock lines. This will insure that the clock's rise and fall times will, on the various traces, remain nearly equal; and PA1 4. Place a maximum of 2 stubs on a given transmission line tap or tie point. The desire here is to maintain a reasonably distributed loading on the clock lines.
As used in this specification, the term "panel board" will be understood to mean any of the above type boards or other boards to come in the future which have the design flexibility of being wired into different configurations by. interconnecting wires or other conductors not part of the printed circuit conductive layers themselves.
A second type of multi-layered printed circuit board (having "dedicated", custom, printed circuit interconnects) has no wire-wrap or other wire interconnect pins and makes all connections using patterns in the various conductive layers of the board. This second type of board usually has the power distribution planes located on the inner layers and many of the clocks and signals on the outer layers. This gives this type of board an advantage over the more general purpose "panel boards" described above which must use the board's outer layers for power and ground distribution.
While the present invention is equally applicable to all types of printed circuit boards, the distinction between "panel" (first type) and "dedicated" (second type) PC boards is made, because special consideration of high speed interconnection schemes have been ignored in panel boards, while some attention has been given to high speed signal distribution for many years in dedicated PC boards.
All of the above may be referred to as "wiring to directly interconnect electronic components". This definition differentiates dedicated printed circuit and panel boards from back plane wiring which simply distributes clocks from board to board.
It is important to recognize that the class of panel boards uses the panel to support the sockets and the decoupling capacitors and uses conductive layers to provide low impedance paths for power and ground. The component's power and ground pins are connected to the required or ground plane by means of solder clips or solder washers which connect the pin's socket to one of the board's outer layers. While this approach virtually guarantees that the components will see good clean power and ground, it rules out the use of the outer layers as a means of distributing clocks and timing signals. The result is that the user must design and maintain the board's clock distribution system using discrete wires or possibly twisted pairs of wires.
A Technician's initial design task involves estimating the propagation delays and adjusting the clock's routing to insure that these delays do not result in contention or conflicts. The main challenge here is keeping track of the clock's propagation delays and of the using device's requirements.
The maintenance of the clock distribution system during test and check out is a far more demanding and error prone task that tends to significantly increase the cost of developing and debugging a new digital system. As a design develops and matures, modifications are required that result in moving clock lines about and adding or deleting loads from the various clock lines. These modifications cause significant changes in the clock's propagation delays which in turn can cause a loss of operating and timing margins. The loss of these margins (the most important of which are data input setup and hold times) cause a digital system to become erratic, lose data, and to be very sensitive to changes in temperature and power supply voltages.
The purpose of an interconnection line in any digital system is to transmit information from one point of the system to another. For many electronic devices, the routing of signals through the conductive paths of a standard printed circuit board causes no difficulty in the integrity of the transmitted signal, since the lines are rather short, usually under 380 mm (15 inches) in length, and the frequency of the signals on the conductive paths can be rather low and may have slow rise and fall times. Moreover, the delay time along the line is of little or no concern, and in the time domain of concern, signal skew from line to line is insignificant. A typical example would be a hand or desk calculator wherein the clock rate for such devices is under 10 MHz.
However, as circuit speeds become faster and clock rates increase, the dynamic behavior of the interconnection line becomes increasingly important. The rise and fall times of logic elements, loading effects, delay times of the signal paths, and various other transient characteristics, all affect reliable operation of the system in which the circuit board is installed. For example, it is not unusual in fairly sophisticated high speed circuitry today to encounter signals with rise and fall times on the order of 1 nanosecond. In this discussion, the phrase "high speed" will refer to a signal having fast rise and fall times (typically between 0.5 and 3 nsec.) and not to the frequency of the signal having such rise and fall times, since the signals themselves may or may not have high frequency (high speed) changing of logic states.
Thus, independent of the frequency of the signal being transmitted along a conductive path in a printed circuit board, it is the leading and trailing edges which cause difficulty in the receiving circuit ascertaining which logic state is intended and what time that logic state occurs. This is due to many factors including "ringing" which occurs at the transition points between the two logic levels in a digital system. If the ringing is too intense, it may cause false triggering of the receiving circuit, for having passed through logical "1" and "0" states one or more times before settling down to its intended logical state level. On the other hand, if certain circuit components are introduced to reduce such ringing, such as series damping resistors, the ringing may be reduced, but the noise threshold of the system is impaired because of the diminishing of the separation between the logic levels at the output of the sending device and the input threshold levels of the receiving device.
An example of a high speed wire-wrap board can be found in the description and drawings of U.S. Pat. No. 4,494,172 in the name of Leary et al. While Leary et al. addresses the problem associated with the need for capacitive filtering the voltage layers in a multi-layered printed circuit board, and proposes to use close spacing of the voltage layers to provide a large distributive capacitance and thereby not require as many discrete isolation capacitors, Leary et al. does not address the problems associated with ringing on the signal lines carrying high speed signals from one component to another on the board. Leary et al. does recognize that high speed switching devices cause voltage spikes in the power lines and suggests a physical arrangement of the voltage planes and insulative layers as well as the interconnection with wire-wrap socket terminals to provide an improved panel board with minimum interference, through the power distribution layer, by the high speed operation of one device affecting the operation of an adjacent electronic device. Other prior patents related to multi-layered printed circuit boards include: U.S. Pat. No. 3,932,932 to Goodman which teaches the use of thick ground and voltage planes and discusses plated-through technology; and U.S. Pat. No. 4,004,196 to Doucet which uses termination resistors in a common single-in-line package and short wire-wrap pins to improve high speed signal transmission. Reference is also made to the article "HIGH-SPEED-CPU DESIGN, 40-MHz CMOS CIRCUITS SEND DESIGNERS BACK TO SCHOOL" in the magazine EDN, Mar. 2, 1992, Pages 67-76.
In the publication "MECL System Design Handbook", 4th edition, distributed by Motorola Semiconductor Products, Inc., Product HB 205, REV. 1, Pages 173-187, a good explanation is given of the problems associated with transmitting high speed signals along interconnecting paths in a digital system.
At Page 176 of the Motorola publication, a discussion of printed circuit board interconnects can be found. The layout rules discussed, however, refer to Motorola's line of MECL (Motorola Emitter Coupled Logic) devices which are in some ways less sensitive than some of the CMOS (Complementary Metal-Oxide-Silicon) devices used in large scale integration circuits. Accordingly, while the layout rules and suggested approaches to solving ringing problems may be different as between MECL and CMOS devices, the theory set forth in the aforementioned Motorola publication is quite adequate to explain the problems and indeed provides a good background discussion and analysis of the problems.
Page 43 of the Motorola MECL SYSTEM DESIGN HANDBOOK introduces the various types of printed circuit board transmission lines in common use. The Motorola publication recognizes that printed circuit board layouts range from the most simple single layer board with wired interconnects to the most elaborate multi-layered board with a complete transmission line environment. The use of conductive planes for maintaining noise free grounds and voltage supplies is recognized and discussed with similar results as those proposed in the Leary, et al. patent. It is also suggested to maintain constant characteristic impedance wherever transmission lines become necessary.
However, only three types of transmission line geometries are proposed by Motorola, representing the state of the art in printed circuit board interconnect technology (MECL SYSTEM DESIGN HANDBOOK, Pages 41-62 and 173-194). The three types of transmission line geometries are:
Each type uses a ground plane or a pair of ground planes.
In the wire over ground arrangement, a wire is simply routed from a source to its destination by laying the insulated wire as close as possible to the ground plane. This is useful for breadboard layouts as well as back plane wiring.
The second and third types of transmission line geometries employ conductive paths for the high speed signal in the makeup of the printed circuit board itself. In the microstrip configuration, a narrow width conductive strip is separated vertically from a ground plane by a dielectric medium. The dimensions of the narrow strip and the spacing relative to the ground plane are controlled to establish a pre-determined characteristic impedance.
The third type of line, a strip line, uses a narrow width conductive strip centered in a dielectric medium between two conducting planes. This type of line is used in multi-layered boards, and according to the Motorola publication (Page 179, right hand column), "is not seen in most systems." Furthermore, the publication goes on to state that "Since most designers need not concern themselves with strip lines, little is presented here about them."
U.S. Pat. No. 3,895,435 to Turner et al. teaches a method for interconnecting multilevel strip line circuitry.
The Motorola publication also has a good discussion on transmission line termination techniques beginning at Page 181. As earlier suggested, the approach to minimizing ringing is to provide proper transmission line termination to prevent reflections on the line so that ringing does not occur. Matching the impedance of the transmission line by a termination network accomplishes this objective.
In addition to line length and transmission line terminations, other factors must be considered in high speed systems. System speed requirements will ordinarily be the limiting factor for maximum fanout of the devices of concern. Capacitance increases with fanout and can cause rise and fall times to slow. Thus, as fanout increases, load capacitance (both device and interconnection capacitance) increases, resulting in longer rise and fall times. Larger fanout will normally result in longer interconnecting lines with their longer line delays, so ringing can become excessive. Under these conditions, use of properly terminated lines will result in best performance. A low impedance high-speed signal distribution system is better for driving the high capacitance loading of a large fanout configuration. Characteristic impedances of about 50 ohms to 100 ohms can be readily achieved using easily attainable manufacturing processes in the creation of transmission line configurations for high speed signal distribution in a printed circuit board. For MECL devices, Motorola appears to suggest a 50 ohm transmission line impedance. However, for CMOS devices it has been found more practical to use a characteristic impedance of closer to 100 ohms.
Unterminated line length for high speed lines must be kept to usually under 150 mm (6 inches), and in order to control ringing, fanout is, as indicated, limited. Moreover, as fanout increases, the maximum line length for interconnecting devices diminishes. In the Motorola publication at Page 51, for example, in using a strip line transmission line arrangement, the maximum line length (i.e. maximum un-terminated length) for a 50 ohm characteristic impedance transmission line must be kept shorter than 115 mm (4.5 inches) for a fanout of 8. When characteristic impedances are higher, on the order of 100 ohms, the same strip line transmission line configuration limits the line length to 53 mm (2.1 inches) for a fanout of 8 and even to 71 mm (2.8 inches) or less for a fanout of 4, such limitations being almost prohibitive, especially in a panel board design where it would be practically impossible to interconnect 8 devices with 71 mm (2.8 inches) of wire, and may be even extremely difficult to accommodate a fanout of 4 with that length of wire.
It should be understood that these severe limitations are equally applicable when interconnecting CMOS devices. The figures given above are representative for the MECL 10,100 series circuits but would apply to most modern CMOS devices because the rise and fall times are about the same for the two types of devices (albeit that device impedances are vastly different). One of the most important technical advancements derived from the present invention is the provision of a predictable clock distribution system that reduces the clock distribution uncertainties to a very minimum. The wiring board shown in the attached drawing is typically approximately 233 mm (9 inches) wide and 220 mm (8.5 inches) long. Wiring boards of this size have their clock lines implemented with discrete wires and have clock wiring runs as long as 1 to 2 meters (40 inches to 80 inches). This results in the board's clock signal having a propagation delay of 6 to 12 nanoseconds which is long compared to the typical device's setup and hold time requirements of 0.5 to 6 nanoseconds. It should be noted that the board used for this example is not large many of today's systems are using wiring boards of 400 mm.times.400 mm (16 inches.times.16 inches) and these boards can easily have clock wire runs of 4 meters (13 feet) or more. In this case the propagation delays are frequently in the 20 to 25 nanosecond range and the checkout and development times tend to soar. Most small or modest digital designs require many man weeks for testing and checkout while the larger boards like the 400.times.400 mm size boards can, and frequently do, require many man months.
It is difficult to quantify, but a very substantial, if not the majority, of the time spent on test and checkout involves problems with the setup and hold times of a device's inputs with respect to clock edges. Logic problems are usually easy to identify and fix. Timing problems, on the other hand, frequently involve a signal that goes true a nanosecond or so too early or too late. The difficulty of localizing this type of error is due to the problem of catching and seeing an event that occurs only at relative long intervals and, in no small part, to the fact that the error or fault tends to appear at a point in the system that is far removed from the place where the error occurred. The result is that the engineers and technicians spend a great deal of their time trouble shooting symptoms instead of causes.
There are several reasons why transmission line arrangements according to the prior art are unable to accommodate long lengths of line without encountering a ringing problem. One is that termination networks were either not used or were inadequate in a panel board environment. Another is that the "transmission line effect" defined by a pair of power planes above and below a thin narrow conductive strip sandwiched between two insulative layers in a "dedicated" PC board does not sufficiently confine the narrow strip with the result that the characteristic impedance varies over the length of the line as the narrow conductive strip passes by, and perhaps parallel to, other signal lines carrying fast changing signal information. Additionally, if the narrow conductive strip is a clock line, it may be influenced significantly by an adjacent clock line which is coplanar with it, since the upper and lower ground planes serve no capacity in isolating the clock lines or any other signal lines from the clock line of concern.
Thus, a narrow width conductive strip sandwiched between two ground planes does not approach the geometric configuration of a standard coaxial cable which has proven to be a very effective means for transmitting high speed signals across many feet of transmission length. Also, the lack of any isolation between clock lines or any other signal lines also represents a far departure from a standard coaxial transmission line in which the outside ground shielding would totally encapsulate and isolate the inner conductor and prevent cross interference between adjacent signal carrying lines. Moreover, in wiring panel boards, the use of embedded transmission line arrangements have not been used heretofore in any configuration.
It is therefore clear that there is a need for an improvement over the prior art printed circuit board arrangements, for the distribution of high speed signals along the signal path, which improvement would more closely approach the characteristics of a classical transmission line and would reduce cost associated with the design and development of digital systems. The present invention fulfills these needs.